Power supply voltages of 3.3 volts are being used for 0.5 micrometer linewidth CMOS technologies, rather than the 5.0 supply voltages of the preceding CMOS technologies, to improve reliability as well as to reduce system power consumption. For subsequent generations of CMOS technologies, a further reduction in power supply voltage and more frequent supply voltage scaling have been predicted.
Major challenges associated with this trend are finding reliable ways to maintain compatibility among systems and circuits operating at different power supply voltages and overcoming difficulties in operating circuits at lower voltages. The latter challenge is a severe constraint for analog and mixed analog-digital systems, especially for precision analog systems. Supply voltage compatibility can be maintained by designing 5 volt I/O circuits into 3.3 volt systems. Subsystems which are difficult to operate at 3.3 volts can be operated at 5 volts. These subsystems are integrated with the 3.3 volt systems. Thus, a single mixed signal CMOS integrated circuit (IC) may incorporate circuits which operate at 3.3 volts and circuits which operate at 5.0 volts.
CMOS transistors optimized for 3.3 volt operation have a thinner gate dielectric layer (typically silicon dioxide) than 5.0 volt transistors in order to reduce short channel effects and to increase the drive current capability of the transistors. When such transistors are operated in 5.0 volt I/O and analog circuits, problems include: (1) the gate oxide wearout phenomenon which limits the maximum operating electric field to 4 MV-cm.sup.-2, as described by M. Kakumu et al in IEEE Trans. Electron Devices, Vol. 37, No. 5, May 1990, pages 1334-1342, and (2) hot electron induced degradation, as described by P. Cottrell et al in IEEE Trans. Electron Devices, Vol. ED-26, 1979, pages 520-533. Oxide wearout can be alleviated by less aggressively scaling the gate oxide thickness for 3.3 volt operation, but at a cost of compromised transistor performance and, consequently, reduced system performance. An approach which avoids this compromise between performance and reliability is integration of two gate oxide thicknesses, one optimized for 5.0 volt transistors and one optimized for 3.3 volt transistors.
A process for forming gate oxides of different thicknesses on a CMOS integrated circuit is disclosed in U.S. Pat. No. 5,047,358 issued Sep. 10, 1991 to Kosiak et al. The disclosed process requires photoresist to come in contact with one of the gate oxide layers, as well as requiring several processing steps between the first gate oxidation and polysilicon gate deposition steps. Thus, the disclosed approach is susceptible to contamination of the gate oxide layers. Other approaches to fabrication of CMOS integrated circuits having high voltage and low voltage transistors are disclosed in U.S. Pat. No. 4,628,341 issued Dec. 9, 1986 to Thomas and U.S. Pat. No. 5,024,960 issued Jun. 18, 1991 to Haken. Another process for forming dielectric layers of different thicknesses is disclosed by A. Ito et al in IEEE Trans. Electron Devices, Vol. 41, No. 7 Jul. 1994, pages 1149-1159.